1. Field of the Invention
The present invention relates to digital computing, and more particularly to an N-NARY design tool for semiconductors that generates both a behavioral model and a physical model of a subcircuit design.
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as the material appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
2. Description of the Related Art
N-NARY logic is a dynamic logic design style fully described in a copending patent application, U.S. patent application Ser. No. 09/019355, filed Feb. 5, 1998, now U.S. Pat. No. 6,066,965, and titled "Method and Apparatus for a N-NARY logic Circuit Using 1-of-4 Signals", which is incorporated herein for all purposes and is hereinafter referred to as "The N-NARY Patent." (The present invention supports one feature of N-NARY logic not disclosed in The N-NARY Patent; that is, null values are supported by the present invention as discussed below.)
The N-NARY logic family supports a variety of signal encodings, including 1-of4. In 1-of4 encoding, four wires are used to indicate one of four possible values. In contrast, traditional static logic design uses two wires to indicate four values, as is demonstrated in Table 1. In Table 1, the A.sub.0 and A.sub.1 wires are used to indicate the four possible values for operand A:00, 01, 10, and 11. Table 1 also shows the decimal value of an encoded 1-of4 signal corresponding to the two-bit operand value, and the methodology by which the value is encoded using four wires.
TABLE 1 2-bit N-NARY N-NARY (1-of-4) operand (1-of-4) Signal A Signal A value Decimal Value 1-of-4 wires asserted A.sub.1 A.sub.0 A A[3] A[2] A[1] A[0] 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 2 0 1 0 0 1 1 3 1 0 0 0
"Traditional" dual-rail dynamic logic also uses four wires to represent two bits, but the dual-rail scheme always requires two wires to be asserted. In contrast, as shown in Table 1, N-NARY logic only requires assertion of one wire. The benefits of N-NARY logic over dual-rail dynamic logic, such as reduced power and reduced noise, should be apparent from a reading of the N-NARY Patent. All signals in N-NARY logic, including 1-of4, are of the 1-of-N form where N is any integer greater than one. A 1-of-4 signal requires four wires to encode four values (0-3 inclusive), or the equivalent of two bits of information. More than one wire will never be asserted for a valid 1-of-N signal. Similarly, N-NARY logic requires that a high voltage be asserted on only one wire for all values, even 0.
Any one N-NARY logic gate may comprise multiple inputs and/or outputs. In such a case, a variety of different N-NARY encodings may be employed. For instance, consider a gate that comprises two inputs and two outputs, where the inputs are a 1-of-4 signal and a 1-of-2 signal and the outputs comprise a 1-of-4signal and a 1-of-3 signal. Variables such as P, Q, R, and S may be used to describe the encoding for these inputs and outputs. One may say that one input comprises 1-of-P encoding and the other comprises 1-of-Q encoding, wherein P equals two and Q equals four. Similarly, the variables R and S maybe used to describe the outputs. One might say that one output comprises 1-of-R encoding and the other output comprises 1-of-S encoding, wherein R equals four and S equals 3. Through the use of these, and other, additional variables, it is possible to describe multiple N-NARY signals that comprise a variety of different encodings.
Supporting a new logic design style requires the invention of new coding techniques to support the computer-aided design of logic circuits and their constituent subcircuits. The N-NARY logic design style is no exception. The need to perform logical verification of circuits as well as provide a means of describing the physical design and interconnectivity of these circuits creates conflicting requirements. Physical circuit descriptions do not accidentally provide automatic means of logically verifying their correctness, and logical descriptions do not accidentally provide information on how each transistor in a circuit is connected to its neighbors.
Logic design tools of the prior art, such as VHDL and Verilog, keep libraries of subcircuits, or cells. These library cells represent significant effort expended to perform two separate tasks. To use the prior art tools, one must first develop a schematic representation of the configuration of the transistors for the cell under design. Second, one must develop a behavioral model of the particular logical operation desired from the cell. In conjunction with this two-step process, there is considerable effort required to verify that the behavioral model and the schematic "match up" to create the desired functionality.
In contrast, the tool of the present invention does not require a semiconductor designer to develop a schematic and a separate behavioral model that must be verified against each other. Instead, the design tool of the present invention separately compiles both a behavioral model and a physical circuit description from one syntax statement. The present invention guarantees that the schematic and the behavioral model will "match up," greatly reducing the man-hours needed to design semiconductor circuits. This process is particularly helpful in the design of N-NARY semiconductor circuits, since the N-NARY logic family creates the opportunity for various physical circuit descriptions that perform the same logical function. The problem of matching a behavioral model with a physical description therefore becomes critical in the context of N-NARY circuit design.